Design Automation for Side Channel and Fault Attack Resistant Lightweight Cryptography

The main constituents of any heterogeneous network are the numerous end devices comprised of embedded or Internet of Things (IoT) devices, constrained by area footprint, memory, processing, and power consumption ratings. Additionally, these devices often process sensitive data that needs to be cryptographically protected against possible leakages to attackers. Therefore, these systems should not only be optimized in terms of classical parameters like power, performance, and area (PPA) but also need to be secured by design. Currently, Side Channel Analysis (SCA) and Fault Attacks (FA) pose a serious threat to these systems, which can either reduce or even eliminate the security levels of an embedded design. Depending on the target implementation sophisticated and advanced attack tools are already available in the market that require just one to a few hundred power measurements to extract the secret keys from a mathematically robust cryptographic implementation. Additionally, it is difficult to implement conventional encryption methods in IoT or embedded devices since they are typically resource-hungry in the public and private key configurations. Hence, novel measures must be adopted and have opened a new field of research known as lightweight cryptography. Therefore, validation and protection against implementation-based attacks, and designing lightweight counter-measures are considered to be of utmost importance and have been added as required design criteria in the National Institute of Standards and Technology (NIST) standardization call for lightweight cryptography. Additionally, a major threat to manufacturing ICs having secure compositions is the fact that most of the time the technology libraries, design components, and Electronic Design Automation (EDA) flows are from third parties. Accordingly, the EDA tools to manufacture Integrated Circuits (ICs) of these embedded systems must also be tuned to handle both the PPA optimizations and security realms in the design process. The classical EDA flows cannot detect side-channel leakages at early design stages or provide countermeasures against FAs and SCAs, let alone optimized countermeasures that have low footprints on power, performance, and area. Moreover, the existing EDA flow optimization techniques could conflict with the security requirements of IC design and provide adversaries with leakage surfaces. Also, in most cases, the security evaluation of ICs (SCA and FA) is carried out at the post-silicon stage incurring a significant loss, if the circuit-under-test is found to be vulnerable. In addition, the role of the EDA tool is pivotal in determining and evaluating countermeasures that suit their needs at the design stage itself in a tight time-to-market constraint. Hence, the primary goal of my work is to see how to reduce overall design cycle time in the tight time-to-market scenario by detecting early security flaws in the designs and adopting state-of-the-art techniques to generate SCA and FA-resistant lightweight IC designs.

 

 

Rajat Sadhukhan is currently serving as a postdoctoral fellow at New York University, Brooklyn, New York. He earned his Ph.D. in the Computer Science and Engineering department at the Indian Institute of Technology Kharagpur in August 2023 under the guidance of Prof. Debdeep Mukhopadhyay. Prior to that, he pursued a B.E. in Information Technology from West Bengal University of Technology (Kolkata) and an M.Sc.(Technology) (sponsored by Intel, Bangalore) in VLSI-CAD from Manipal Academy of Higher Education (Bangalore) in 2008 and 2015 respectively. Rajat’s journey into academia was preceded by a tenure as a Component Design Engineer at Intel, Bangalore from 2008 to 2016. His research interest includes cryptography, hardware security, and VLSI design.