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Biosketch
Sandeep Chandran is an Assistant Professor in the Department of Computer Science and Engineering at Indian Institute of Technology (IIT) Palakkad. He received his PhD from IIT Delhi where he received the IIT Delhi FITT award for Best Industry Relevant PhD. Prior to joining the Institute, he was a Senior Design Engineer at AMD where he was part of the performance modelling team that designed the Zen microarchitecture. He was also a Research Intern in the Silicon Bring-up Team at Freescale Semiconductors (now NXP semiconductors). His research interests are in areas of design and verification of high-performance systems.
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Research
I investigate both the design and verification aspects of scaling high-performance systems. On the design front, my research focuses on using a combination of modern architectures (where there is a reconfigurable fabric alongside a processor), and system-level modifications to increase single-thread performance beyond state-of-the-art processors without compromising the energy-efficiency and security of the system. On the verification front, I focus on techniques to make debugging faster and privacy-aware.
Current Students
- Mr. Sumesh (Internal PhD Candidate, co-supervised by Dr. Chandrashekar, Jul 2019 - Present)
- Ms. Amrutha Benny (PhD student, January 2020 - Present)
- Ms. Harshitha C (MS student, January 2020 - Present)
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Teaching
Current Semester:
CS5107: Programming Lab
CS3010: Operating Systems
CS3110: Operating Systems Lab
Previous Semesters:
CS5619: Synthesis of Digital Systems
CS5005: Parallel Programming
CS2160: Computer Organization Lab
CS1020: Introduction to Programming
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Additional Information
TitlePublicationsDescription
Invited Book Chapter
- Debug Data Reduction Techniques by Sandeep Chandran, and Preeti Ranjan Panda, in Post-silicon Validation and Debug, SPRINGER 2018
Journals
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Managing Trace Summaries to Minimize Stalls During Post-silicon Validation
Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Ayan Bhattacharyya, Deepak Chauhan, and Sharad Kumar, IEEE TRANSACTIONS ON VLSI SYSTEMS (TVLSI), VOLUME 25, ISSUE 6, JUNE 2017 -
Area-aware Cache Update Trackers for Post-silicon Validation
Sandeep Chandran, Smruti R. Sarangi, and Preeti Panda, IEEE TRANSACTIONS ON VLSI SYSTEMS (TVLSI), VOLUME 24, ISSUE 5, MAY 2016 -
Architectural Support for Handling Jitter in Shared Memory based Parallel Applications
Sandeep Chandran, Prathmesh Kallurkar, Parul Gupta, and Smruti R. Sarangi, IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS (TPDS). VOLUME 25, ISSUE 5, MAY 2014
Conferences
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DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring by Neetu Jindal, Sandeep Chandran, Preeti Ranjan Panda, Sanjiva Prasad, Abhay Mitra, Kunal Singhal, Shubham Gupta, and Shikhar Tuli, ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC'19), Las Vegas, USA, 2019
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Extending Trace History Through Tapered Summaries in Post-silicon Validation
Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Deepak Chauhan, Sharad Kumar, ACM/IEEE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASPDAC'16), Macao SAR, CHINA, 2016 (Best paper award candidate) -
A Generic Implementation of Barriers using Optical Interconnects
Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda and Smruti R. Sarangi, ACM/IEEE INTERNATIONAL CONFERENCE ON VLSI DESIGN (VLSID’16), Kolkata, India, 2016. -
Space Sensitive Cache Dumping for Post Silicon Validation
Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda, ACM/IEEE DESIGN AUTOMATION AND TEST IN EUROPE (DATE’13), Grenoble, France, 2013.
TitleOther InformationDescriptionAwards and Recognitions
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IIT Delhi FITT Award for Best Industry Relevant PhD 2017-18
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AMD Spotlight Award for Q3 2017
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Best Paper Award Nomination at ASP-DAC 2016
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Outstanding Teaching Assistant award for two consecutive semesters
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TCS Research Scholar Fellowship (Scholarship for 4 years)
Technical Services
- TPC member of VLSID'20, and VDAT'20
- TPC member and Session chair of VLSID'19
- TPC member of HiPC'19
- Reviewer - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
- Reviewer - IEEE Embedded Systems Letters
- Reviewer - International Journal of Parallel Programming (IJPP)
- Reviewer - Integration - the VLSI journal (Elsevier)
- Reviewer - Several editions of conferences such as DAC, ICCAD, DATE, ASPDAC, VLSID, ISLPED, and ESWEEK
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Publications
Neetu Jindal, Sandeep Chandran, Preeti Ranjan Panda, Sanjiva Prasad, Abhay Mitra, Kunal Singhal, Shubham Gupta, and Shikhar TuliACM/IEEE Design Automation Conference (DAC'19) (2019)DHOOM.pdf (754.35 KB)Sandeep Chandran, and Preeti Ranjan Pandain Post-silicon Validation and Debug (eds. Prabhat Mishra, Farimah Farahmandi), Springer (2018)Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Ayan Bhattacharyya, Deepak Chauhan, and Sharad KumarIEEE Transactions on VLSI Systems (TVLSI) 25 (6) (2017)Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda and Smruti R. SarangiACM/IEEE International Conference On VLSI Design (VLSID’16) (2016)Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Deepak Chauhan, Sharad KumarACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC'16) (2016)Sandeep Chandran, Smruti R. Sarangi, and Preeti PandaIEEE Transactions on VLSI Systems (TVLSI) 24 (5) (2016)Sandeep Chandran, Prathmesh Kallurkar, Parul Gupta, and Smruti R. SarangiIEEE Transactions on Parallel and Distributed Systems (TPDS) 25 (5) (2014)Sandeep Chandran, Smruti R. Sarangi, and Preeti Ranjan PandaACM/IEEE Design Automation and Test in Europe (DATE’13) (2013)
